1. Field of the Invention
The present invention relates to semiconductor packages encapsulating semiconductor chips connected to substrates and boards. The present invention also relates to lead frames for use in semiconductor packages.
The present application claims priority on Japanese Patent Application No. 2004-372919, the content of which is incorporated herein by reference.
2. Description of the Related Art
Conventionally, there are available a variety of semiconductor packages such as QFN (Quad Flat Non-Leaded) packages having plural leads partially exposed on terminal surfaces and side surfaces lying in thickness directions of molded resin bodies. An example of a conventionally-know semiconductor package is disclosed in Japanese Unexamined Patent Application Publication No. 2002-314024. FIG. 14 shows the layout of a lead frame 51 for use in a QFN package, which is produced using a lead frame 51 including a stage 55 for mounting a semiconductor chip 53 thereon, plural leads 57 formed in the periphery of the stage 55, and dam bars 59 for interconnecting the leads 57 together. The lead frame 51 is produced by performing press working and/or etching on a thin metal plate.
In the manufacturing of the lead frame 51, the semiconductor chip 53 is bonded onto the surface of the stage 55 first; then, pads of the semiconductor chip 53 are electrically connected to the leads 57 via bonding wires 61. Next, as shown in FIG. 15, a molded resin body 63 is formed to integrally fix the semiconductor chip 53, the stage 55, the bonding wires 61, and the bonded portions of the leads 57 therein. Herein, a backside 57 of the lead 57 is formed in the same plane with a backside 63a of the molded resin body 63.
The lead 57 is partially subjected to plating with respect to a surface 57b and a backside 57a, which are exposed to the exterior of a QFN package, thus forming a plated layer 65 for soldering. The plated layer 65 is used to improve the anti-wetting ability of solder for the lead 57. Lastly, the dam bar 59 and a projecting portion 57c of the lead 57 projecting to the exterior are subjected to cutting along a cutting line A, thus completing the manufacturing of a QFN package in which the leads 57 are electrically independent from each other.
The aforementioned QFN package (denoted by a reference numeral 80) is mounted on a board 71 in such a way that, as shown in FIG. 16, the backside 57a of the lead 57 and a land 73 of the board 71 are bonded together via a solder 67. This allows the QFN package 80 to be electrically connected to the board 71. The joining strength realized by the solder 67, by which the lead 57 and the land 73 are joined, depends upon the overall area of the backside 57a of the lead 57, which is exposed to a lower surface 63a of the molded resin body 63.
Due to recent tendencies regarding microelectronics and devices, there is a demand for improvement of reliability regarding electric connections established between QFN packages and boards. In the case of the QFN package 80 connected to the board 71, the overall area of the backside 57a of the lead 57, which are exposed to the lower surface 63a of the molded resin body 63, is restricted by prescribed standards; hence, it is very difficult to improve the joining strength between the lead 57 and the land 73 by way of a simple increase of the overall area of the backside 57a of the lead 57. In other words, under the present circumstances, it is very difficult to further improve reliability regarding electric connection between the QFN package 80 and the board 71.